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dc.contributor.authorTena, E.-
dc.contributor.authorCastro, Javier-
dc.contributor.authorAcosta, Antonio José-
dc.identifierdoi: 10.1109/JETCAS.2014.2315878-
dc.identifierissn: 2156-3357-
dc.identifier.citationIEEE Journal on Emerging and Selected Topics in Circuits and Systems 4: 203- 215 (2014)-
dc.description.abstractCryptocircuits can be attacked by third parties using differential power analysis (DPA), which uses power consumption dependence on data being processed to reveal critical information. To protect security devices against this issue, differential logic styles with (almost) constant power dissipation are widely used. However, to use such circuits effectively for secure applications it is necessary to eliminate any energy-secure flaw in security in the shape of memory effects that could leak information. This paper proposes a design methodology to improve pull-down logic configuration for secure differential gates by redistributing the charge stored in internal nodes and thus, removing memory effects that represent a significant threat to security. To evaluate the methodology, it was applied to the design of AND/NAND and XOR/XNOR gates in a 90 nm technology, adopting the sense amplifier based logic (SABL) style for the pull-up network. The proposed solutions leak less information than typical SABL gates, increasing security by at least two orders of magnitude and with negligible performance degradation. A simulation-based DPA attack on the Sbox9 cryptographic module used in the Kasumi algorithm, implemented with complementary metal-oxide-semiconductor, SABL and proposed gates, was performed. The results obtained illustrate that the number of measurements needed to disclose the key increased by much more than one order of magnitude when using our proposal. This paper also discusses how the effectivenness of DPA attacks is influenced by operating temperature and details how to insure energy-secure operations in the new proposals. © 2014 IEEE.-
dc.titleA Methodology for optimized design of secure differential logic gates for DPA resistant circuits-
dc.description.versionPeer Reviewed-
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