DSpace Community:http://hdl.handle.net/10261/902024-03-28T08:29:13Z2024-03-28T08:29:13ZReliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of agingSantana-Andreo, A.Saraza-Canflanca, P.Castro-López, R.Roca, ElisendaFernandez, F. V.Fernández, Francisco V.http://hdl.handle.net/10261/3482002024-03-25T21:47:29Z2024-02-23T12:25:48ZTítulo: Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging
Autor: Santana-Andreo, A.; Saraza-Canflanca, P.; Castro-López, R.; Roca, Elisenda; Fernandez, F. V.; Fernández, Francisco V.
Resumen: Physical Unclonable Functions (PUFs) have gained attention as a lightweight hardware security primitive. In particular, the SRAM-based PUF uses the unpredictable power-up value of the cells within an SRAM. Although these values should ideally be always the same within each SRAM to accomplish a correct PUF operation, this is often not the case, especially when factors like circuit aging are considered. While certain studies explore the effects of aging on SRAM PUFs, they often simplify the analysis. For instance, some studies assume that only Bias Temperature Instability (BTI) contributes to circuit degradation while others evaluate the overall degradation without accounting for the stochastic effects of aging on each individual cell. In this work, we first perform a detailed characterization of the nature of aging in SRAM PUFs, demonstrating that the impact of Non-Conductive Hot-Carrier Injection cannot be neglected. We also show that different cells degrade differently, highlighting the importance of accounting for the stochasticity of aging. After that, a method based on the Data Retention Voltage metric to select the cells with the most stable power-up response is introduced. Using these cells to generate the PUF identifier will result in a more stable response, and thus a better PUF performance.2024-02-23T12:25:48ZCharacterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic PathsVan Santen, Victor M.Gata-Romero, José M.Núñez, JuanCastro-López, R.Roca, ElisendaAmrouch, Hussamhttp://hdl.handle.net/10261/3481962024-03-02T02:53:07Z2024-02-23T12:18:35ZTítulo: Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths
Autor: Van Santen, Victor M.; Gata-Romero, José M.; Núñez, Juan; Castro-López, R.; Roca, Elisenda; Amrouch, Hussam
Resumen: Bias Temperature Instability (BTI) and Hot-Carrier Degradation (HCD) are key aging mechanisms, frequently studied with transistor measurements or inverter-based (INV) Ring Oscillators (RO) measurements. However, large-scale digital circuits are typically manufactured with standard cells (such as logic gates). In a reliability simulation flow (e.g., SPICE-based standard cell characterization with degraded transistors), many assumptions about the standard cells have to be made (such as load capacitance, signal slews, uncertainty in aging models, etc.) and can lead to high simulation uncertainty. In this work, we propose to verify this standard cell characterization with standard cell oscillator measurements in silicon. For this purpose, we present the following novel contributions: 1) The first work with BTI and HCD measurements of heterogeneous oscillators (multiple different cell types in one RO) based on logic paths extracted from processors. 2) The first work exploring the impact of BTI and HCD on oscillators containing combinational standard cells, i.e. single cells incorporating multiple logic gates (such as And-Or-Inverter (AOI) cells and Or-And-Inverter (OAI)) and cells performing complex actions such as full-adders.
Descripción: Trabajo presentado en el 2023 IEEE International Reliability Physics Symposium (IRPS), 26-30 March 2023, Monterey, CA, USA .2024-02-23T12:18:35ZPACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit DesignsPassos, FabioLourenco, NunoRoca, ElisendaMartins, RicardoCastro-López, R.Horta, NunoFernández, Francisco V.http://hdl.handle.net/10261/3475662024-03-25T22:46:47Z2024-02-19T18:26:20ZTítulo: PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs
Autor: Passos, Fabio; Lourenco, Nuno; Roca, Elisenda; Martins, Ricardo; Castro-López, R.; Horta, Nuno; Fernández, Francisco V.
Resumen: In this paper, the application of regression-based supervised machine learning (ML) methods to the modeling of integrated inductors and transformers is examined. Different ML techniques are used and compared to improve accuracy. However, it is demonstrated that none of the ML techniques considered provided good results unless a smart modeling strategy, tailored to the specific design problem, is used. Taking advantage of these modeling strategies, high accuracy can be obtained when compared to full-wave electromagnetic (EM) simulations (less than 2% error) and experimental measurements (less than 5% error). The most accurate model, obtained by the appropriate combination of an ML technique and modeling strategy, has been integrated into a tool called PACOSYT. The tool uses optimization algorithms to allow the designer to obtain an inductor/transformer with optimal performances in just seconds while keeping the accuracy of EM simulations. Furthermore, the tool provides the passive component S parameter description file for seamless use in circuit simulations. The tool can be used standalone or integrated with design frameworks, like Cadence Virtuoso or AIDASoft, a framework for circuit optimization. To illustrate the different usages of the tool, several passive devices are synthesized, and hundreds of millimeter-wave power amplifiers are synthesized using AIDASoft together with PACOSYT. The tool has been developed using open-source Python frameworks and does not use any closed-source licenses. PACOSYT, which also allows other designers to create their models for different technologies, is made publicly available.2024-02-19T18:26:20ZSelf-modifiable image processing library for model-based design on FPGAsGarcés-Socarrás, Luis ManuelCabrera Sarmiento, Alejandro JoseSánchez-Solano, SantiagoBrox Jimenez, PiedadIeno, EgidioPimenta, Tales Cleberhttp://hdl.handle.net/10261/3466002024-03-23T22:04:10Z2024-02-09T23:16:49ZTítulo: Self-modifiable image processing library for model-based design on FPGAs
Autor: Garcés-Socarrás, Luis Manuel; Cabrera Sarmiento, Alejandro Jose; Sánchez-Solano, Santiago; Brox Jimenez, Piedad; Ieno, Egidio; Pimenta, Tales Cleber
Resumen: This paper describes highly configurable hardware modules, included in XIL XSGImgLib library, capable of speed up the hardware implementation of video and image processing systems using the model-based design flow provided by Xilinx System Generator. As part of this work, generic architectures were developed to exploit specific characteristics of some processing blocks, which can be self-modified using a novel software procedure developed for MATLAB®. This procedure, along with the generic architecture and the configuration options, allows the abstraction about the specific details of the hardware implementation, as well as the adjustment of the resources consumption of the high-speed image and video processing application for embedded systems with weight, volume and power consumption constrains like smart cameras, video surveillance and autonomous vehicles. The use of this video and image processing library is illustrated by the development of a segmentation application on a Spartan-6 LX45 FPGA although any Xilinx's FPGA is supported.2024-02-09T23:16:49Z