TY - JOUR
ID - Digital.CSIC
A1 - Delgado Restituto, Manuel
A1 - Fernández-Bootello, Juan Francisco
A1 - Rosa Utrera, José Manuel de la
A1 - Ruiz Amaya, Jesús
Y1 - 2005-11
UR - http://hdl.handle.net/10261/3847
N2 - This paper describes the design of a 12-bit
80MS/s Digital-to-Analog converter implemented in a 0.13?m CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The converter is segmented in an unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distributed in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Transistor-level simulation results show that the Spurious-Free Dynamic-Range
is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher than 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 active area.
KW - Current Steering
KW - Digital-to-Analog Converters
T1 - A 0.13?m CMOS Current Steering D/A Converter for PLC and VDSL Applications
ER -