2024-03-29T01:49:44Zhttp://digital.csic.es/dspace-oai/requestoai:digital.csic.es:10261/35742016-02-16T02:20:55Zcom_10261_90com_10261_4col_10261_343
A CMOS 0.8- µm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion
Rosa, José M. de la
Pérez-Verdú, Belén
Río, Rocío del
Rodríguez-Vázquez, Ángel
Analog-to-digital conversion
ΣΔ modulation
Switched-currentΔΣ
This paper presents a CMOS 0.8-/spl mu/m switched-current (SI) fourth-order bandpass /spl Sigma//spl Delta/ modulator (BP-/spl Sigma//spl Delta/M) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z/sup -1//spl rarr/-z/sup -2/) to a 1-bit second-order low-pass /spl Sigma//spl Delta/ modulator (LP-/spl Sigma//spl Delta/M). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz.
2008-04-14T17:27:46Z
2008-04-14T17:27:46Z
2000-08-01
artículo
IEEE Journal of Solid-State Circuits 35(8): 1220-1226 (2000)
0018-9200
http://hdl.handle.net/10261/3574
10.1109/4.859514
eng
http://dx.doi.org/10.1109/4.859514
openAccess
Institute of Electrical and Electronics Engineers