2024-03-29T15:32:18Zhttp://digital.csic.es/dspace-oai/requestoai:digital.csic.es:10261/1563452022-09-27T06:38:49Zcom_10261_90com_10261_4col_10261_343
Yousefzadeh, Amirreza
Jabłonski, Mirosław
Iakymchuk, T.
Linares-Barranco, Alejandro
Rosado, Alfredo
Plana, Luis A.
Temple, Steve
Serrano-Gotarredona, Teresa
Furber, Steve B.
Linares-Barranco, Bernabé
2017-10-17T08:59:39Z
2017-10-17T08:59:39Z
2017
IEEE Transactions on Biomedical Circuits and Systems, 11(5): 1133-1147 (2017)
http://hdl.handle.net/10261/156345
10.1109/TBCAS.2017.2717341
Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links for each physical LVDS connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs attaining a maximum event transmission speed of 75 Meps (Mega events per second) for 32-bit events at a line rate of 3.0 Gbps. Full HDL codes (vhdl/verilog) and example demonstration codes for the SpiNNaker platform will be made available.
eng
openAccess
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems
artículo