2024-03-29T00:27:23Zhttp://digital.csic.es/dspace-oai/requestoai:digital.csic.es:10261/1804052021-06-30T11:28:01Zcom_10261_90com_10261_4col_10261_469
DIGITAL.CSIC
author
Quintero, Héctor
author
Jiménez Través, Manuel
author
Avedillo, M. J.
author
Núñez, Juan
2019-04-23T12:05:59Z
2019-04-23T12:05:59Z
2018-07-02
2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
http://hdl.handle.net/10261/180405
10.1109/SMACD.2018.8434921
Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design.
eng
openAccess
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines
comunicación de congreso
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URL
https://digital.csic.es/bitstream/10261/180405/1/C3.pdf
File
MD5
f7d8b93c7bd6b1e55fadef60e5658331
232982
application/pdf
C3.pdf