2024-03-29T07:31:17Zhttp://digital.csic.es/dspace-oai/requestoai:digital.csic.es:10261/1700212021-06-10T15:20:46Zcom_10261_90com_10261_4col_10261_469
DIGITAL.CSIC
author
Vornicu, Ion
author
Carmona-Galán, R.
author
Rodríguez-Vázquez, Ángel
2018-09-21T09:23:48Z
2018-09-21T09:23:48Z
2018
IEEE Sensors Journal , 18(4): 1576-1584 (2018)
http://hdl.handle.net/10261/170021
10.1109/JSEN.2017.2784484
CMOS image sensors based on single-photon avalanche-diodes (SPAD) are suitable for 2D and 3D vision. Limited by uncorrelated noise and/or low illumination conditions, image capturing becomes nearly impossible in a single-shot exposure time. Moreover, the depth accuracy is affected by jitter. Therefore, many frames need to be taken to reconstruct the final accurate image. The proposed reconstruction algorithm is based on pixel-wise histogram building. Specifically, a histogram is built on the fly for each pixel of the array from the ongoing acquired frames. This paper presents the design and implementation on FPGA of a real-time pixel-wise inter-frame histogram builder at 1 kfps. The design has been proven with a 64 × 64-pixels SPAD camera. Its remarkable robustness has been demonstrated in harsh conditions, such as 42 kHz of dark count rate (DCR) and high background illumination up to 20 times larger than the DCR. The system has a graphic user interface for 2D/3D imager configuration, image streaming, and pixel-wise histogram streaming.
eng
openAccess
Real-Time Inter-Frame Histogram Builder for SPAD Image Sensors
artículo
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URL
https://digital.csic.es/bitstream/10261/170021/1/ifHB_sensors_journal_ivornicu_fv.pdf
File
MD5
e07bbb4637bfb6dbaa3b260cee74a863
2914190
application/pdf
ifHB_sensors_journal_ivornicu_fv.pdf